The present invention relates to a semiconductor device and a fabrication method for the same. In particular, the present invention relates to a semiconductor device that can be made finer and also has shallow-junction, low-resistance diffused layers, and a fabrication method for such a semiconductor device.
With the tendency of higher integration of semiconductor integrated circuits, finer MIS transistors have been demanded. To respond to this demand, MIS transistors having shallow-junction, low-resistance extension diffused layers are required.
A conventional fabrication method for a semiconductor device will be described with reference to FIGS. 9A to 9E (see Japanese Laid-Open Patent Publication No. 2002-76136, for example).
FIGS. 9A to 9E are cross-sectional views for sequentially illustrating process steps of a conventional fabrication method for a semiconductor device.
In the step shown in FIG. 9A, arsenic (As) ions and phosphorus (P) ions as n-type impurities are implanted in a p-type semiconductor substrate 200. The resultant substrate is subjected to heat treatment, to form an n-type channel diffused layer 203 containing arsenic impurities in the top portion of the semiconductor substrate 200 and an n-type well layer 204 containing phosphorus impurities in a portion under the n-type channel diffused layer 203.
In the step shown in FIG. 9B, a silicon oxide film and a polysilicon film are sequentially formed on the resultant semiconductor substrate 200, and then patterned by photolithography and dry etching, to form a gate oxide film 201 and a gate electrode 202.
In the step shown in FIG. 9C, As ions as n-type impurities are implanted in the semiconductor substrate 200 using the gate electrode 202 as a mask, to form n-type pocket implanted layers 207A. Subsequently, boron (B) as p-type impurities are implanted in the semiconductor substrate 200 using the gate electrode 202 as a mask, to form p-type extension implanted layers 206A.
In the step shown in FIG. 9D, a silicon nitride film is deposited over the entire top surface of the semiconductor substrate 200 and then etched by anisotropic etching, to form sidewalls 208 on the walls of the gate electrode 202.
In the step shown in FIG. 9E, boron difluoride (BF2) molecular ions as p-type impurities are implanted in the semiconductor substrate 200, to form high-density source/drain implanted layers. The resultant substrate is subjected to high-temperature, short-time heat treatment, to form p-type high-density source/drain diffused layers 205, p-type extension diffused layers 206 and n-type pocket diffused layers 207.
In the conventional fabrication method for a semiconductor device, the boron implantation energy for formation of the p-type extension implanted layers 206A is made lower than usual in the process of forming the p-type extension diffused layers 206, to thereby attain a shallow junction.
As described above, in the conventional fabrication method for a semiconductor device, boron is implanted in the semiconductor substrate 200 under low-energy, high-dose implantation conditions, to form the p-type extension implanted layers 206A having a shallow junction.
The conventional method described above however has a problem as follows. During the high-temperature, short-time heat treatment performed after the boron implantation, boron in the semiconductor substrate 200 is subjected to a phenomenon of transient enhanced diffusion (hereinafter, referred to as TED). Due to the TED, boron is diffused deep into a region beyond a predetermined junction in the semiconductor substrate 200, and this results in failure to give a desired impurity profile to the p-type extension diffused layers 206. The transient enhanced diffusion (TED) as used herein refers to an abnormal diffusion phenomenon in which impurity atoms interact with excessive point defects such as interstitial silicon atoms and atomic vacancies existing in the semiconductor substrate, resulting in enhancement of diffusion of the impurity atoms. The excessive point defects are mainly introduced by implantation damage occurring during ion implantation in many cases.
Hence, in the conventional fabrication method for a semiconductor device described above, even though the ion implantation energy is lowered to attain a shallower junction, the TED of implanted dopants increases. Therefore, it is difficult to form MIS transistors having shallow-junction, low-resistance extension diffused layers only by implanting ions of a single element at a low energy.